This invention relates to a semiconductor device comprising a plurality of bipolar transistors.
As the packing density of a semiconductor integrated circuit is increased, the electrodes of the circuit occupy more area. To further increase the packing density, it is necessary to reduce the area occupied by the electrodes. The packing density of MOS integrated circuit is improved by using impurity-doped polysilicon films as at least gate electrodes. A polysilicon film gate, which is generally known as "silicon gate", can easily be formed in a multilayer structure, thus providing a great latitude of design.
Polysilicon films are seldom used for electrodes in a bipolar integrated circuit. In this specification electrode means also interconnection. Aluminum films are used because a bipolar device differes from a MOS device in an operation mechanism and the structure. First, electric currents flow through the emitter, base and collector of the bipolar device, whereas no gate current flows through the MOS device. Secondly, the bipolar device has diffusion layers of both conductivity types, i.e. diffusion layers of P type and diffusion layers of N type. By contrast, the MOS device has diffusion layers of only N type if it is an N-channel device or diffusion layers of only P type if it is a P-channel device.
Since a base current flows through it, the bipolar device must have low resistance base electrodes. Otherwise it would fail to operate. Therefore the electrodes are generatly aluminum films, not polysilicon films. On the other hand, since no gate current flows through it, the MOS device may have relatively high resistance gate electrodes. This is why polysilicon films which have a higher resistance than aluminum films are used for gate electrodes in an MOS device.
Since the bipolar device has diffusion layers of both conductivity types, PN junction would be formed in many cases between the P diffusion layers and the N diffusion layers if the electrodes are made of polysilicon. If such PN junctions are formed, the bipolar device will cease to function. This problem does not occur in the MOS device whose diffusion layers are of either P type or N type.
It is difficult, however, to form a multilayer structure of aluminium films. Further it is difficult to arrange aluminum films in the desired pattern. Therefore in the known bipolar device, aluminum films are so arranged as to provide so-called "single layer electrodes". The bipolar devices cannot have their packing density improved.
Integrated injection logic gates (IIL gates) are well-known bipolar devices. IIL gates are popular because they are logic gates which have a low power consumption. An IIL gate comprises an upwards vertical transistor for an inverter and a transistor for an injector. The injector transistor is complimentary to the inverter transistor and applies a load on the base of the inverter transistor. The injector transistor is a lateral transistor, whose collector and base are respectively the base and emitter of the inverter transistor. The electrodes of the IIL gates are aluminum films. Until now it has not been through possible to construct IIL gates whose electrodes are made of polysilicon. As mentioned above, as it is difficult to form aluminum films one upon another, the packing density of the IIL gates cannot be increased.
When closely studied, an IIL gate is found to possess the following characteristic features. First, its logic amplitude is small, and its operating current is extremely small. Secondly, in the electrode connecting a P layer of one IIL gate and an N layer of another IIL gate, current flows always from the P layer to the N layer. The IIL gate has such a structure as shown in FIG. 1 which is a cross sectional view.
As shown in FIG. 1, a buried N.sup.+ layer 14 is formed on a P.sup.- substrate 12. On the substrate 12 and the buried N.sup.+ layer 14 an N epitaxial layer 16 is formed. Formed in the N epitaxial layer 16 is an N.sup.+ diffusion layer 18 which contacts the busied N.sup.+ layer 14. Two P diffusion layers 20 and 22 are formed in that portion of the N epitaxial layer 16 which is laid on the N.sup.+ layer 14. In the P diffusion layer 22 two N.sup.+ diffusion layers 24 and 26 are formed. The N.sup.+ diffusion layer 18 is connected to the ground GND, and the P diffusion layer 20 is connected to a power source voltage +E. The P diffusion layer 22 is connected to an input terminal IN. The N.sup.+ type diffusion layers 24 and 26 are connected to output terminals OUT.sub.1 and OUT.sub.2, respectively.
FIG. 2 is an equivalent circuit diagram of the IIL gate shown in FIG. 1. An NPN vertical transistor Q.sub.1 for an inverter consists of the N layer 16 which serves as an emitter, the P layer 22 which serves as a base and the N.sup.+ layers 24 and 26 which serve as collectors. A PNP lateral transistor Q.sub.2 consists of the P layer 20 which serves as an emitter, the N layer 16 which serves as a base and the P layer 22 which serves as a collector. The IIL gate may be represented by such a symbol as shown in FIG. 3. Then, a T type flip-flop comprised of IIL gates will be illustrated in FIG. 4.
As shown in FIG. 4, to connect the input terminal (i.e. P layer) of, for example, an IIL gate 32 to the output terminal (i.e. N layer) of the adjacent IIL gate 34, an electrode is necessary. Now, current flow in such electrodes of an integrated circuit which comprises IIL gates will be discussed, and reference will be made to FIG. 5.
FIG. 5 is a schematical plan view of an integrated circuit comprising a plurality of IIL gates, of which only three, i.e. IIL gates 36.sub.1, 36.sub.2 and 36.sub.3, are illustrated. Electrodes connecting these IIL gates 36.sub.1, 36.sub.2 and 36.sub.3 are also shown in FIG. 5. The IIL gate 36.sub.1 has a P layer 38.sub.1, an N.sup.+ layer 40.sub.1 and a P layer 42.sub.1. Similarly, the IIL gate 36.sub.2 has a P layer 38.sub.2, an N.sup.+ layer 40.sub.2 and a P layer 42.sub.2, and the IIL gate 36.sub.3 has a P layer 38.sub.3, an N.sup.+ layer 40.sub.3 and a P layer 42.sub.3. The P layers 38.sub.1, 38.sub.2 and 38.sub.3 are each the base (i.e. signal input terminal) of an inverter transistor. The N.sup.+ layers 40.sub.1, 40.sub.2 and 40.sub.3 are each the collector (i.e. signal output terminal) of the inverter transistor. The P layers 42.sub.1, 42.sub.2 and 42.sub.3 are each the emitter of an injector transistor. They are generally called "injectors". Hereinafter they will be called "injector P layers".
An electrode film 44.sub.1 is formed and connects the N.sup.+ layer 40.sub.1 of the IIL unit 36.sub.1 to the P layer 38.sub.2 of the IIL gate 36.sub.2. Likewise, an electrode film 44.sub.2 is formed and connects the N.sup.+ layer 40.sub.2 of the IIL gate 36.sub.2 to the P layer 38.sub.3 of the IIL gate 36.sub.3. Further provided is an electrode film 46 which connects the injector P layer 42.sub.1 of the IIL gate 36.sub.1, the injector P layer 42.sub.2 of the IIL gate 36.sub.2 and the injector P layer 42.sub.3 of the IIL gate 36.sub.3.
As long as the inverter transistor of the IIL gate 36.sub.1 is conductive, its base current flows from the injector P layer 42.sub.1 and its collector current flows through the base (i.e. P layer 38.sub.2) of the inverter transistor of the next IIL gate 36.sub.2. The inverter transistor of the IIL gate 36.sub.2 still remains non-conductive. When the inverter transistor of the IIL gate 36.sub.2 is rendered conductive, its collector current flows through the base (i.e. P layer 38.sub.3) of the IIL gate 36.sub.3. That is, in the electrode film 44.sub.1 connecting the N.sup.+ layer 40.sub.1 to the P layer 38.sub.2 current flows in the direction of arrow A.sub.1, from the P layer 38.sub.2 to the N.sup.+ layer 40.sub.1. And in the electrode film 44.sub.2 connecting the N.sup.+ layer 40.sub.2 to the P layer 38.sub.3 current flows in the direction of arrow A.sub.2, from the P layer 38.sub.3 to the N.sup.+ layer 40.sub.2.